FOR IMMEDIATE RELEASE
CynApps Adds Cyn++ to Open-Source Toolbox
Eases Transition to High-Level Design and Verification
SANTA CLARA, Calif - Oct. 17, 2000 - CynApps, the methodology leader in
C/C++ based design and verification, added to the EDA community's
open-source toolbox today by making its Cyn++ macro preprocessor
available under an open-source license at (www.cynapps.com). Cyn++
simplifies the job of describing hardware in C++ for those used to
working with Verilog and VHDL. Designers can now freely download the
company's original open source offering, the Cynlib C++ class library for
design and verification, and Cyn++ on the CynApps website.
Cyn++, a bridge between traditional HDLs and C++, enables HDL designers
to code in a syntax similar to that of Verilog or VHDL and still take
advantage of the higher-level features of C/C++. The preprocessor's
output is standard Cynlib/C++, but this is transparent to the logic
designer since the simulation and debugging environment is related
directly to the Cyn++ code.
"Cyn++ substantially lowers the barrier to writing hardware models in
C++, making it unique in the high-level language arena," said Dr. John
Sanguinetti, president of CynApps. "We have been demonstrating it at
trade shows for the past year, and virtually everyone who's tried it can
go from Verilog to C++ effortlessly. Cyn++ is a perfect complement to
Cynlib, so making it available under an open-source license is a natural
thing to do."
Rationale for Transitioning to C++
The majority of system architects and software engineers already use
C/C++ for their system modeling and software programs, although they are
generally unfamiliar with hardware design at the register-transfer level.
Logic designers can benefit from using C++ with a class library such as Cynlib because it provides a
higher level of abstraction than VHDL or Verilog as well as a platform
for enterprise-wide, free simulation. CynApps offers a complete unified
design and verification environment using Cynlib/C++ that has evolved
from a standard HDL design flow.
Since announcing availability of its Cynlib open-source C++ hardware
design library and simulator last year, thousands of engineers worldwide
have downloaded the software. Additional momentum is clearly
demonstrated by the fact that dozens of companies, including the biggest
names in EDA, IP, semiconductors, and systems design, have now endorsed
C++ as the only viable, next-generation design language.
Pricing and Availability
The latest versions of Cyn++ and Cynlib, which includes an RTL simulator,
are freely available under open-source licenses and can be downloaded
directly from the CynApps website. A professional support package is
also available by contacting the company at info@cynapps.com. Platforms
supported include Solaris, Linux, HP and Windows.
About CynApps
CynApps was founded in 1998 to develop tools to support the use of
higher levels of abstraction for hardware design. By enabling C++ to be
used as a hardware description language through the development of the
Cynlib® class library, CynApps has eliminated the need to manually
rewrite an algorithm using a language such as Verilog or VHDL prior to
synthesis. Cynlib is available under an open-source license. The company
now offers a complete tool suite that supports successive elaboration of
an abstract C/C++ description into a hardware description, to be
synthesized automatically. The Cynlib environment is the most complete
C++ design environment available today. CynApps has its worldwide
headquarters in Santa Clara, Calif. and can be reached at (408) 588-4000,
or on the web at www.cynapps.com.
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